The present invention generally relates to semiconductor structures, and more particularly to p-type field effect transistor (p-FET) devices having a strained silicon-germanium (SiGe) channel, and a method for making the same.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. At the core of FETs, a channel region is formed in an n-doped or p-doped semiconductor substrate on which a gate structure is formed. Depending whether the on-state current is carried by electrons or holes, the FET comes as an n-FET device or a p-FET device. The overall fabrication process may include forming a gate structure over a channel region connecting source-drain regions within the substrate on opposite sides of the gate, typically with some vertical overlap between the gate and the source-drain region.
An option for continued scaling of planar FETs to the 22 nm node and beyond may be building these devices on an extremely thin semiconductor-on-insulator (ETSOI) substrate. However, fin field effect transistors (FinFETs) and nanowire channel FETs are becoming more widely used, primarily because they may offer better performance than planar FETs at the same power budget.
FinFETs are three dimensional (3-D), fully depleted metal-oxide semiconductor field effect transistor (MOSFET) devices having a fin structure formed from the semiconductor substrate material. The fins may extend between the device source and drain surrounding the channel region forming the bulk of the semiconductor device. The gate structure may be located over the fins covering the channel region. Nanowire FETs, also referred to as gate-all-around (GAA) FETs, may include a source region, a drain region and nanowire channels between the source-drain regions. In this case, the gate may enfold the nanowire channels regulating electron flow through the nanowire channels between the source-drain regions. FinFETs and nanowire FETs architecture may allow for a more precise control of the conducting channel by the gate, significantly reducing the amount of current leakage when the device is in off state.
In the particular case of p-type FET devices, or p-FET devices, a silicon-germanium (SiGe) channel may help achieve the appropriate near band-edge workfuncion to enhance device performance.